1. Technical Field
The invention relates generally to semiconductor device fabrication, and more particularly, to methods of fabricating a passive element while eliminating interlevel chemical mechanical polishing (CMP) in back-end-of-line (BEOL) processes.
2. Background Art
In the semiconductor fabrication industry, passive elements such as thin film resistors or metal-insulator-metal (MIM) capacitors are typically formed in dielectrics in back-end-of-line (BEOL) layers. BEOL refers to the portion of the integrated circuit fabrication where the active components (transistors, resistors, etc.) are interconnected with wiring on the wafer. BEOL processes typically employ a “damascene process” in which an interconnect pattern is first lithographically defined in a layer of interlevel dielectric, then metal is deposited to fill the resulting trenches, and then excess metal is removed by chemical-mechanical-polishing (CMP) (planarization). Planarization of the interlevel dielectrics in the BEOL layers is required for formation of passive elements.
This situation presents a number of challenges. First, known CMP processes do not allow for dielectric interlevel planarization of BEOL layers for current technologies, e.g., 65 nm. For example, FIG. 1 shows a semiconductor device including a thin film resistor 10 including a first silicon carbon nitride (SiCN) layer 12 of thickness T and a tantalum nitride (TaN) layer 14 having a thickness T. A silicon oxide (SiO2) layer 16 of thickness T and a second SiCN layer 18 of thickness T/2 are under resistor 10. Together, resistor 10 and underlying layers 16 and 18 may have a total thickness of 3.5T. Resistor 10 is positioned within a dielectric layer 20, e.g., of silicon oxide (SiO2). A metal wire 22 and contact via 24 extend through dielectric layer 20 to an underlying layer 26, e.g., a first metal layer, and each have a thickness 3T (not shown for clarity). CMP of interlevel dielectric layer 20 typically requires 2.5T height removal to fully planarize the layer. Hence, this height removal requirement prevents usage of passive elements at early BEOL layers for current technologies because CMP would destroy resistor 10. In addition, CMP would induce scratches, defects, and height variability for contact via(s) 24, and is incompatible with many dielectrics for current technologies. One approach to this problem is to position resistor 10 in later BEOL layers away from first metal layer, e.g., layer 26, with thicker wires, but this technique is undesirable due to thermal issues, i.e., the need to place the resistor close to the silicon substrate to increase heat dissipation, wiring layout, or other reasons. In another approach, resistor 10 is positioned within a silicon layer or a first metallization layer. However, this is disadvantageous because thermal and other issues, such as cross-talk, typically prevent use of the silicon layer, and use of the first metallization layer creates physical interference issues for interconnects.
A second challenge to formation of passive elements in BEOL layers is presented by the fact that equipment for BEOL equipment, which typically does not include CMP tools for interlevel dielectrics, is typically isolated from front-end-of-line (FEOL) equipment that includes CMP tools for dielectrics. BEOL processing typically requires tools for planarization of metals, not dielectrics. As a result, fabrication of passive elements in the BEOL layers requires providing potentially duplicate tools for the BEOL process and the FEOL process, due to concerns about metallic or mobile ion contamination of FEOL processes and tools. The expense of this requirement is prohibitive.